搜索资源列表
32mips-cpu
- 基于32为MIPS指令设计的cpu，32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
Ship_based_on_dual_CPU_design_generator_protection
- 基于双CPU的船舶发电机保护测控装置设计Ship based on dual CPU design generator protection and monitoring device-Ship based on dual CPU design generator protection and monitoring device
RISC_SPM
- 简单risc cpu设计，本人通过书中的代码，又加了一些，已通过仿真。-Risc cpu simple design, I code by the book, but also added some, has been through simulation.
CPU
- mips系列，CPU的Verilog语言设计，自己写的-mips series, CPU of the Verilog language design, to write their own
access_hardware
- 实例演示了DELPHI 检测计算机硬件如：cpu，内存，磁盘，光盘，显示器模式、端口、电池，鼠标等的方法，源码设计比较详尽。-DELPHI examples demonstrate the detection of computer hardware, such as: cpu, memory, disk, CD, display mode, port, battery, mouse, and other methods, a more detailed source design.
DiSyLab4
- A simple 8085 cpu design
myCPU
- CPU design file, design using quatus II. It can simulate data file.
POC-Project
- 系统总线与打印机之间的借口：并行输出控制器POC的设计。涉及POC与CPU，POC与printer之间的握手操作。-Between the system bus and an excuse for the printer: parallel output controller POC design. Involved in POC and CPU, POC and the printer handshake between the operations.
CPU
- CPU亲和性代码，案例中2个CPU可以根据情况自己设计-CPU affinity code, case 2 the situation can design their own CPU
CPU-tool-chain-design
- 摘要：EDA技术的成熟和进步，缩短了微处理器硬件设计和综合的周期。同时，开发工具链设计的自动化，已成了高效率、高质量嵌入式微处理器设计的重要内容。本文提出了采用体系结构描述语言(ADL)实现微处理器开发工具链自动设计的有效方法。针对ADL描述流水线的局限性，进行了扩展改进，因而使改进后的ADL能用来直接描述流水线。新方法在CK幸CORE开发工具链设计中的应用表明，比用GNU工具链功效有了显著提高。-Abstract: EDA technologies mature and progress, r
zxcpu
- 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a R
cpu
- 一个CPU设计的实验，设计了一个很简单的CPU-Experimental design of a CPU, designed a very simple CPU
MSP430-to-CPU-card-interface-
- MSP430单片机与CPU卡接口函数设计-MSP430 MCU and CPU card interface function design
A-RISC-Design
- RISC设计：MIPS指令集控制器核，详细介绍一款32位risc-cpu。-A RISC Design:Synthesis of the MIPS Processor Core
vhdl_16CPU
- 16位CPU设计，采用VHDL语言，自带测试汇编语言，能实现基本运算和移位、跳转等操作-16-bit CPU design, using VHDL language, self-test assembly language, to achieve the basic operations and shift operations such as jump
cpu
- 以ISE为平台设计的单时钟CPU，实现最基本的5条指令（R、LW、SW、BEQ、J） -ISE as a platform to design single-clock CPU, 5 to achieve the most basic instructions (R, LW, SW, BEQ, J)
cu
- 基于quartus的CPU设计中核心部件，控制存储器的架构-Quartus CPU design based on the core components, control memory architecture
CPU
- CPU 课程设计 加减移位 与或等操作 挺有用的哦-CPU and or curriculum design operations such as addition and subtraction shift quite used oh
cpu
- 单周期和流水dsp cpu的设计 及foword的插入-Single-cycle and water dsp cpu plug design and foword
cpu_verilog_vhdl
- CPU核verilog、VHDL实现（两个8051带文档 ， or12000 ） 以及cpu设计教程-Personal collection of the CPU core (with two 8051 documents, or12000) plus cpu design tutorials